The present invention relates to a virtual computer system and more particularly to a technology for speeding up a switching of address translation tables in a guest operating system (guest OS).
As the number of servers employed increases, a server operation becomes increasingly complicated, giving rise to an operation cost. As one technology to reduce the server operation cost, a server integration that integrates a plurality of servers into a single server is drawing attention. Among technologies for realizing the server integration, a virtual machine technique is known which logically divides one computer with an arbitrary ratio. In the virtual machine technique, firmware (or middleware) such as hypervisor divides a physical computer into a plurality of logical partitions (LPAR: Logical PARtition) and allocates computer resources (computer processing unit (CPU), main memory and input/output device (I/O)) to each LPAR to allow individual operating systems to run on their associated LPARs. Alternatively, the virtual machine technique involves running a host operating system (the operating system that directly uses the physical machine) on a single server and causing the hypervisor on the host operating system (host OS) to perform the similar dividing operation to allow a plurality of guest operating systems (the operating systems that run on the host operating system) to run on their associated LPARs. The virtual machine technique enables a plurality of operating systems that conventionally run on a plurality of servers and software running on these operating systems to run on a single server, thus realizing a server integration.
The virtual machine technique, which has conventionally been used in large computers such as main frame computers, are finding its use also in low-end servers and personal computers as the performance of microprocessors has improved in recent years.
Computers such as servers that employ the virtual machine technique have a plurality of virtual machines to run guests (generally referring to guest OSs and software running on the guest OSs) and a virtual machine monitor (VMM) that controls the virtual machines.
In realizing the server integration by the virtual machine technique, a plurality of guests to be integrated need to be provided with independent memory spaces. Shown in FIG. 2 is an example of address translation setting that the VMM performs on the physical machine to allow the guest OSs to make settings on the virtual machine and to use independent memory spaces.
The VMM divides a physical memory space (host physical memory space 215) in the host to create memory spaces, from memory space 217 for guest 0 to memory space 218 for guest n, and allocates the divided memory spaces to the respective guests. While, as shown in the memory space 217 for guest 0, the host physical memory spaces allocated to the guests may not necessarily have an address 0 as a start point, the guest OSs are created by assuming that the address 0 is a start point. So, the VMM needs to generate a memory space (guest physical memory space 205) that sets an address 0 used by each guest as a start point and to transform an address of the guest physical memory space 205 into an address of the host physical memory space 215.
As for the address conversion, a CPU (10-v, 10-p) generally has, as a mechanism for high-speed address conversion, a page table (PT) pointer register (60-v, 60-p) that holds a position of a PT defining a correspondence between a pre-conversion address and a post-conversion address, and a TLB (Translation Lookaside Buffer) (50-v, 50-p) holding a part copy of the PT. The CPU (10-v, 10-p) performs high-speed address conversion using information in the TLB (50-v, 50-p). The guest OS uses this mechanism to realize a virtual memory.
The guest OS generates a guest PT-a (70-a) defining the correspondence between an address of guest virtual memory space 201 and an address of guest physical memory a (206) and registers an address of the guest PT-a (70-a) with the PT pointer register (60-v) in the CPU (10-v) of the virtual machine. Then, the guest OS and a process running on the guest OS perform memory operations by specifying addresses in the guest virtual memory space 201. When the guest OS wants to access the guest physical memory space 205, it specifies an identical transformation to the guest PT-a (70-a) to access the guest virtual memory space 201.
To have a TLB (50-p) of the CPU (10-p) perform the address conversion required for the operation of the guest, the VMM takes advantage of what has been described above, i.e., creates a shadow PT-a (80-a) defining the correspondence between the address of the guest virtual memory space 201 and the address of the host physical memory a (216) and registers the address of the shadow PT-a (80-a) with the PT pointer register (60-p) in accordance with the content of the guest PT-a (70-a) that the guest OS was going to register with the PT pointer register (60-v) of the virtual machine.
The guest OS generally prepares a guest virtual memory space for each process running on the guest OS. Thus, the guest OS creates a guest PT corresponding to each process. In switching processes, the guest OS registers an address of the guest PT corresponding to a switched process with the PT pointer register.
Since the content of the shadow PT depends on the content of the guest PT, when the guest OS updates a guest PT address, the VMM needs to operate the shadow PT to have the CPU perform an appropriate address conversion.
An example of the address translation setting in the physical machine for a guest PT after a process switching is shown in FIG. 3. Since the guest substituted a guest PT-b (70-b) for the PT pointer register (60-v), changing the correspondence between the guest virtual memory space 201 and a guest physical memory b (306), the VMM prepares a shadow PT-b (80-b) defining the correspondence between the guest virtual memory space 201 and a host physical memory b (316) and registers an address of the shadow PT-b (80-b) with the PT pointer register (60-p).
As a method for preparing the shadow PT-b (80-b), U.S. Pat. No. 6,606,697 discloses a method in which, each time the updating of the guest PT address is detected, the VMM refers to the guest PT-b (70-b) after process switching and rewrites all the settings of the shadow PT-a (80-a) to create the shadow PT-b (80-b).
U.S. 2002/0082824 discloses a method that reduces the number of entries of shadow PTs to be rewritten. In this method, each time it detects the updating of the guest PT address, the VMM disables all entries of the shadow PT-a (80-a) and makes them a temporary shadow PT-b (80-b). When it is necessary to enable the entries of the shadow PT-b (80-b) for continued operation of the guest, the CPU (10-p) generates an exception and the VMM, using this exception as a trigger, selectively creates only an entry of the shadow PT-b (80-b) required for the memory operation of the guest.
In these existing methods, the VMM rewrites the shadow PT each time it detects the updating of the guest PT address. So, if the same guest PT is used many times as when two guest PTs are alternately used, the processing of the VMM becomes redundant. Generally, since the guest PT is often used repetitively many times, this redundancy will result in an increased time required to update the guest PT address.
In light of the above problems, the present invention is intended to shorten the time it takes to update the guest PT address, i.e., to enhance the speed of the update processing.